gateflow

Codebase architect - maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Examples: "map this codebase", "document the architecture", "show module hierarchy"

Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"

Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.

SystemVerilog learning mode - generates exercises, reviews solutions

SystemVerilog lint checker with structured output. Runs Verilator lint, categorizes errors/warnings, explains issues, returns parseable result block for orchestration.

Intent router and expand mode orchestrator for GateFlow. Classifies user intent semantically, determines confidence, triggers expand mode for ambiguous requests, and hands off to appropriate skill/agent.

SystemVerilog simulator with structured output. Auto-detects DUT vs testbench, compiles with Verilator, runs simulation, returns parseable result block for orchestration.

Summarize Verilator/lint output in a readable format

Testbench verification best practices and patterns. This skill provides architecture guidance, verification methodology, and examples for writing professional-quality testbenches. Examples: "testbench best practices", "how to structure TB", "verification patterns"