gf-sim

# GF Sim Skill

Compile and run SystemVerilog simulation with structured output.

## Instructions

### 1. Identify Files

**If files specified in args:**
Use provided paths. First file is typically the testbench.

**If no files specified:**
Auto-detect by scanning for SV files:

```bash
ls *.sv rtl/*.sv tb/*.sv 2>/dev/null
```

### 2. Classify Files: DUT vs Testbench

**Testbench indicators** (has any of):
- `initial begin`
- `$display`, `$monitor`
- `$finish`, `$fatal`
- `$dumpfile`, `$dumpvars`
- Clock generation: `always #N clk = ~clk`
- File in `tb/` directory or named `*_tb.sv`, `tb_*.sv`

**DUT indicators** (has any of):
- `always_ff`, `always_comb`
- Synthesizable constructs only
- No `$` system tasks (except assertions)
- File in `rtl/` directory

**Quick classification:**
```bash
# Files with testbench markers
grep -l '\$display\|\$finish\|initial begin' *.sv 2>/dev/null

# Files with DUT markers
grep -l 'always_ff\|always_comb' *.sv 2>/dev/null
```

### 3. Compile with Verilator

```bash
verilator --binary -j 0 -Wall --trace <dut-files> <testbench> -o sim
```

**Notes:**
- DUT files listed first, testbench last
- `--trace` enables VCD waveform generation
- `-o sim` names the output executable

**If multiple top modules detected:**
```bash
verilator --binary -j 0 -Wall --trace --top-module <tb_name> <files> -o sim
```

### 4. Run Simulation

```bash
./obj_dir/sim
```

Or if named differently:
```bash
./obj_dir/V<top_module>
```

### 5. Parse Results

**Check output for:**
- `PASS`, `SUCCESS`, `All tests passed` -> PASS
- `FAIL`, `ERROR`, `MISMATCH`, `ASSERT` -> FAIL
- `$fatal` or non-zero exit code -> FAIL
- `$finish` reached without errors -> PASS

**Check exit code:**
```bash
./obj_dir/sim
echo "Exit code: $?"
```
- Exit 0: Success
- Non-zero: Failure

### 6. Return Structured Result

**ALWAYS end your response with this exact block format:**

```
---GATEFLOW-RESULT---
STATUS: PASS|FAIL|ERROR
ERRORS: <count>
WARNINGS: <count>
FILES: <comma-separated list>