Testbench verification best practices and patterns. This skill provides architecture guidance, verification methodology, and examples for writing professional-quality testbenches. Examples: "testbench best practices", "how to structure TB", "verification patterns"
View on GitHubFebruary 2, 2026
Select agents to install to:
npx add-skill https://github.com/codejunkie99/Gateflow-Plugin/blob/main/plugins/gateflow/skills/tb-best-practices/SKILL.md -a claude-code --skill tb-best-practicesInstallation paths:
.claude/skills/tb-best-practices/# Testbench Best Practices
Professional verification patterns for SystemVerilog testbenches.
## Layered Testbench Architecture
```
┌─────────────────────────────────────────┐
│ Test Layer │ ← Test scenarios
├─────────────────────────────────────────┤
│ Environment Layer │ ← Agent coordination
├──────────────┬──────────────────────────┤
│ Agent │ Agent │ ← Protocol-specific
│ ┌────────┐ │ ┌────────┐ │
│ │ Driver │ │ │Monitor │ │
│ └────────┘ │ └────────┘ │
│ ┌────────┐ │ ┌────────┐ │
│ │Sequencer│ │ │Scoreboard│ │
│ └────────┘ │ └────────┘ │
├──────────────┴──────────────────────────┤
│ Interface Layer │ ← Signal abstraction
├─────────────────────────────────────────┤
│ DUT │
└─────────────────────────────────────────┘
```
---
## 1. Testbench Structure
### Basic Self-Checking TB
```systemverilog
module tb_dut;
// Clock and reset
logic clk = 0;
logic rst_n = 0;
always #5 clk = ~clk;
// DUT signals
logic [7:0] data_in, data_out;
logic valid_in, valid_out;
// DUT instance
dut u_dut (.*);
// Test
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb_dut);
// Reset
rst_n = 0;
repeat(5) @(posedge clk);
rst_n = 1;
// Stimulus + Check
for (int i = 0; i < 100; i++) begin
@(posedge clk);
data_in <= $urandom();
valid_in <= 1;
@(posedge clk);
valid_in <= 0;
// Wait for output
wait(valid_out);
check_result(data_in, data_out);
end
$display("TEST PASSED");
$finish;
end
// Checker
function void check_result(input [7:0] expected, input [7:0] actual);
assert(actual == expected)
else $er